LVDS Cable Selection Guide: Impedance, Pinout, and Cable Construction

Selecting an LVDS cable for Camera Link, FPD-Link, or FPGA-to-FPGA links comes down to four electrical and mechanical specifications:

Key Takeaways

• LVDS requires 100 Ω ± 10% differential impedance per TIA/EIA-644-A — tighter ±5% tolerance for runs above 1 Gbps or beyond 5 meters, TDR-validated.
• Intra-pair skew must stay below 20 ps/m for reliable 1 Gbps operation; inter-pair skew below 50 ps/m for parallel LVDS interfaces like Camera Link Full or FPD-Link III bidirectional.
• Shielded twisted pair (STP) and twinax constructions dominate LVDS cabling — STP for runs under 5 m at 1 Gbps; individually-shielded twinax for longer runs or rates above 2 Gbps.
• Connector and pinout selection is application-specific — Camera Link uses MDR/SDR-26, automotive FPD-Link III uses HSD or FAKRA, FPGA backplane LVDS uses Samtec QTH or high-density board-to-board connectors.
• IPC/WHMA-A-620 Class 2 acceptance for LVDS cables requires TDR impedance documentation, eye-diagram or BERT test data at the rated rate, plus continuity and hi-pot per the standard.

Engineering rule of thumb: For LVDS data rates up to 1 Gbps with runs under 3 meters, specify 100 Ω ± 10% STP — beyond that, the link budget collapses on impedance and skew unless you upgrade to ±5% individually-shielded twinax.

Differential Impedance: Why 100 Ω, and How Tolerance Drives Eye-Diagram Margin

LVDS is defined by TIA/EIA-644-A as a differential signaling scheme with 100 Ω terminated transmission lines, 350 mV nominal differential swing, and 1.2 V common-mode. Impedance is matched at both the source and receiver — any deviation in the cable's differential characteristic impedance creates a reflection that degrades signal integrity.

Cable impedance tolerance directly affects eye-diagram margin. A 100 Ω ± 10% cable can have ±10 Ω discontinuities, each producing roughly 5% voltage reflection — at LVDS's 350 mV swing, that's 17.5 mV per discontinuity, a significant fraction of the receiver's typical 100 mV sensitivity threshold at 1+ Gbps.

For data rates above 1 Gbps or runs beyond 5 meters, specify ±5% tolerance and validate with TDR at multiple points. The twisted-pair impedance guide covers the relationship between conductor geometry, dielectric constant, and characteristic impedance in detail.

Intra-Pair and Inter-Pair Skew: The Two Budget Items Engineers Miss

Differential signaling rejects common-mode noise only when both conductors of a pair arrive at the receiver simultaneously. Time delay between the two conductors — intra-pair skew — converts the differential signal partially into common-mode noise and reduces the eye opening.

Intra-pair skew in good LVDS cable is typically below 10 ps/m. For 1 Gbps (1000 ps unit interval), industry-typical practice limits intra-pair skew to under 20 ps/m end-to-end; 2+ Gbps applications require 5 ps/m. Skew is driven by length matching at conductor stranding and by uniform dielectric around each conductor.

Inter-pair skew matters for parallel LVDS interfaces carrying related data — Camera Link Medium and Full configurations, FPD-Link III bidirectional links, and parallel display interfaces. Inter-pair skew above 50 ps/m forces de-skew logic at the receiver or limits the maximum data rate of the slowest channel.

Skew is one of the most common reasons LVDS cables passing impedance and continuity testing still fail eye-diagram acceptance. Specify both intra-pair and inter-pair tolerances as separate line items.

Cable Construction: STP, Twinax, and Drain-Wire Geometry

Three constructions cover most LVDS applications, distinguished by how each pair is shielded and how the drain wire is terminated.

Shielded Twisted Pair (STP) wraps each twisted pair in aluminum-polyester foil with a drain wire, then bundles pairs inside an overall braid. Standard for Camera Link Base/Medium runs under 5 meters. The foil provides ~60 dB attenuation across 30 MHz–1 GHz; the overall braid handles external EMI. The EMI shielding comparison covers the foil-versus-braid trade.

Twinax (individually-shielded coaxial pair) uses two parallel coaxial-style conductors with individual foil shields and drain wires, often with an overall braid. Used for high-speed LVDS above 2 Gbps (Camera Link Full, FPD-Link IV, high-speed FPGA backplane) where the controlled-impedance discipline of coaxial geometry outperforms twisted-pair tolerance.

Drain-wire termination is the most overlooked LVDS specification — the drain wire must be bonded to chassis ground at the receiver for shield-current return. Unterminated drain wires act as antennas and inject common-mode noise via capacitive coupling. The shield grounding guide covers the single-point vs. multi-point decision for LVDS.

For a hybrid custom cable assembly carrying LVDS plus DC power, an inner shielded sub-bundle for the LVDS pairs prevents supply switching noise from coupling into the high-speed pairs.

Connector and Pinout Standards: Camera Link, FPD-Link, MDR, Hirose, JAE

LVDS connector selection is application-driven — the same 100 Ω cable terminates to different connector standards depending on the host system.

Camera Link uses the MDR-26 (Mini D Ribbon) connector on the camera side and SDR-26 on the frame grabber per AIA Camera Link rev 2.0. Base, Medium, and Full configurations populate different pair counts within the 26-pin connector: 4 data pairs plus 1 clock for Base, 8+1 for Medium, 12+1 for Full.

FPD-Link III and FPD-Link IV (Texas Instruments) use HSD or FAKRA Z-key connectors in automotive applications, where the automotive cable assembly must withstand vibration, humidity, and temperature cycling per AEC-Q200 and equivalent automotive specs.

FPGA-to-FPGA backplane LVDS typically uses Samtec QTH/QSH high-density board-to-board connectors or Molex Impel, terminated as a custom Samtec high-speed wire harness. These specify per-pin impedance and crosstalk values that must be matched at the cable interface.

M-LVDS (Multipoint-LVDS, TIA/EIA-899) uses the same cable standards but with different transceiver levels and multi-point termination. Cable selection follows the same impedance and skew rules; pinout is application-specific.

LVDS connector selection affects signal integrity and assembly cost. Common families used in custom LVDS harnesses:

• Hirose DF series — fine-pitch, gold-plated; standard in a Hirose wire harness for industrial sensors and machine vision
• JST GH / SH / SR — small form factor; common in embedded systems and medical devices
• Molex Pico-Clasp / Pico-EZmate — board-to-wire for compact LVDS pairs
• Samtec QStrip / Final Inch — high-density, impedance-characterized connectors for >1 Gbps designs
• Amphenol Mini-IO — locking versions for automotive and ruggedized industrial

Pinout convention is critical. Differential pairs must occupy adjacent pins (P/N on consecutive positions) to maintain electromagnetic coupling between the conductors. If the connector mapping splits a pair across non-adjacent pins or different rows, common-mode noise rejection collapses and skew accumulates. Verify the receiver pin map matches the transmitter pin map before specifying the cable assembly — pinout errors are the most common cause of LVDS link failure on first build.

Cable Length, Data Rate, and Pre-Emphasis Tradeoffs

LVDS cable length is bounded by skin-effect attenuation, dielectric loss, and receiver input sensitivity. For un-equalized links, industry-typical maximums: 5 m at 1 Gbps over STP, 10 m at 1 Gbps over twinax, 5 m at 2 Gbps over twinax, 7 m at 2.5+ Gbps over twinax with pre-emphasis.

For longer runs, transmitter pre-emphasis and receiver equalization compensate for cable loss. Most modern LVDS SerDes chips include programmable pre-emphasis (2–6 dB) and equalization (CTLE or DFE) to extend usable cable length by 50–100% over the un-equalized maximum.

For LVDS assemblies at the edge of the length-vs-data-rate budget, specify the cable's S21 insertion loss at the operating Nyquist frequency rather than length alone — cable loss at 500 MHz (the 1 Gbps Nyquist) is more directly relevant than physical length beyond 5 meters.

LVDS Application-to-Cable Specification Matrix

Specification FAQ

What differential impedance does LVDS require, and what tolerance is acceptable?

LVDS requires 100 Ω differential characteristic impedance per TIA/EIA-644-A, with tolerance typically ±10% for runs up to 1 Gbps and ±5% above 1 Gbps or beyond 5 meters. Validate impedance with TDR at multiple points — both raw cable and connector termination contribute to the profile.

How tight does intra-pair skew need to be for 1 Gbps LVDS?

For 1 Gbps LVDS (1000 ps unit interval), intra-pair skew should remain below 20 ps/m end-to-end including connector contribution. For 2 Gbps and faster, target 5–10 ps/m. Skew is set by cable stranding and dielectric uniformity around each conductor — specify both as separate line items.

When should I specify individually-shielded twinax vs. overall-shielded STP?

Twinax is required when data rates exceed 2 Gbps per pair, cable length exceeds 7 meters at 1 Gbps, or the cable runs near aggressive aggressors (motor drives, switching supplies, RF transmitters). STP suffices for Camera Link Base under 5 meters, FPGA backplane links under 3 meters, and any LVDS application below 1 Gbps in a moderate EMI environment.

Can the same cable serve Camera Link and FPD-Link applications?

The 100 Ω electrical specification is identical, so the same raw cable can serve both. Differences are connectorization (MDR-26 for Camera Link vs. HSD/FAKRA for automotive FPD-Link), pinout assignment, and environmental requirements — Camera Link is lab/industrial; automotive FPD-Link requires AEC-Q200 components, wider temperature range, and vibration testing.

What MOQ and lead time apply to custom LVDS cable assemblies with TDR test data?

Prototype quantities (under 25 units) with TDR documentation typically deliver in 3–5 weeks. Production runs (500+) move to dedicated impedance-controlled extrusion and run 6–10 weeks. MOQ is driven by twinax pair count — single-pair twinax usually has lower MOQ than multi-pair constructions. Provide the target data rate, connector at each end, environmental conditions, and required test documentation (TDR, eye diagram, BERT) for a specific quote.

LVDS cable selection is fundamentally a controlled-impedance, controlled-skew problem with application-specific connector and pinout requirements. For data rates up to 1 Gbps over short runs, 100 Ω ± 10% STP with documented intra-pair skew is the engineering default; beyond that, individually-shielded twinax with TDR-validated ±5% impedance and pre-emphasis-capable transceivers becomes necessary. Specify impedance tolerance, intra-pair and inter-pair skew, and connector pinout as independent line items — continuity and hi-pot pass-through alone is not sufficient for high-speed LVDS acceptance.